Branch instruction handling in a self-timed marking system
Abstract
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.
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