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C.J. Myers
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Verification of timed circuits with failure-directed abstractions
Efficient verification of hazard-freedom in gate-level timed asynchronous circuits
Efficient algorithms for exact two-level hazard-free logic minimization
Cell library for automatic synthesis of analog error control decoders
Synchronous interlocked pipelines
Direct synthesis of timed circuits from free-choice STGs
An asynchronous instruction length decoder
Timed circuit verification using TEL structures
Interfacing synchronous and asynchronous modules within a high-speed pipeline
Interfacing synchronous and asynchronous modules within a high-speed pipeline
Stochastic cycle period analysis in timed circuits
Timed state space exploration using POSETs
Direct synthesis of timed asynchronous circuits
Architectural synthesis of timed asynchronous systems
Direct synthesis of timed asynchronous circuits
Stochastic cycle period analysis in timed circuits
POSET timing and its application to the synthesis and verification of gate-level timed circuits
Verification of delayed-reset domino circuits using ATACS
Timed circuit synthesis using implicit methods
Average-case optimized technology mapping of one-hot domino circuits
Covering conditions and algorithms for the synthesis of speed-independent circuits
An asynchronous implementation of the maxlist algorithm
Efficient timing analysis algorithms for timed state space exploration
Technology mapping of timed circuits
Automatic synthesis of gate-level timed circuits with choice
Synthesis of timed asynchronous circuits
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